The Validation Lead is responsible for driving end-to-end validation strategy across semiconductor chip programs at LTSCT, covering both pre-silicon testability planning and post-silicon functional validation. With 15+ years of experience, the role ensures chips meet design specifications by influencing architecture for testability, preparing robust validation environments, executing comprehensive test plans, and leading defect analysis. This position requires a strong blend of hardware, firmware, and software expertise, along with leadership in cross-functional collaboration to ensure chips are ready for engineering samples and customer deployment. |
SECTION III: KEY RESPONSIBILITIES/ ACCOUNTABILITIES | |
Pre-Silicon Testability |
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Validation Environment Preparation |
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Post Silicon Test Validation |
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Defect Identification & Debugging |
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Leadership & Strategy |
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SECTION IV: KEY INTERACTIONS | |
Internal Stakeholder | Purpose of Interaction |
Chip Architecture & Design Teams |
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Board Design Team |
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Software / firmware Team |
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External Stakeholder | Purpose of Interaction |
Customers (Limited) |
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Source: Larsen & Toubro careers — Read the original posting and apply
This role is listed by the employer on its own careers site. Kaam Ki Khoj does not process applications for it.
Larsen & Toubro is an employer in the Construction/Engineering sector with operations in India. This is a directory listing maintained by Kaam Ki Khoj so that candidates can find the organisation; it is not an official company page and Kaam Ki Kh... Read More
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