Analysis skills
SIT scenario design support, defect triage, and functional root-cause analysis.
Analysis skills
SIT scenario design support, defect triage, and functional root-cause analysis.
1. Expert proficiency in SoC architecture and design, with in-depth knowledge of Verilog and UVM for digital verification.
2. Excellent understanding of C and C++ development as applied to embedded systems and SoC integration.
3. Strong familiarity with RTL design, simulation tools (e.g., Synopsys VCS, Cadence), and advanced verification methodologies.
4. Advanced proficiency in developing and reviewing testbench architectures using UVM.
5. Solid experience in mentoring technical teams and driving best practices in SoC development.
Source: HCLTech careers — Read the original posting and apply
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