Roles & Responsibilities Senior Engineer – Emulation, LTSCT Role Summary Execute and own FPGA prototyping and emulation activities for complex SoC designs, with primary focus on multi-FPGA prototyping, synthesis/P&R, timing closure, bitfile generation, board bring-up and system-level debug. Support emulator model bring-up on ZeBu/Veloce and collaborate with Design, DV, Firmware and Board teams to resolve issues. Drive assigned technical workstreams, automation and productivity improvements while providing hands-on technical guidance to junior engineers. Roles & Responsibilities • Execute end-to-end FPGA prototyping and emulation activities for SoC/ASIC designs, covering RTL preparation, synthesis, partitioning, P&R, bitfile generation, board bring-up and validation. • Take ownership of FPGA prototype model bring-up on platforms such as HAPS, Protium and other FPGA-based prototyping systems. • Support multi-FPGA partitioning and implementation, including partition optimization, FPGA resource utilization, inter-FPGA connectivity, pin utilization and routing challenges. • Perform FPGA synthesis, P&R and timing analysis, identify implementation bottlenecks and work on resolving timing violations, congestion and resource issues. • Support clock and reset implementation for FPGA prototypes, including analysis of ASIC clock structures and development/application of appropriate FPGA constraints. • Drive FPGA board bring-up and debug, including JTAG, clocks, resets, memories and SoC interfaces such as SPI, I2C, UART, MDIO, PCIe and other relevant interfaces. • Develop, generate and validate FPGA bitfiles and support deployment on prototype hardware. • Perform emulator model bring-up and validation on platforms such as ZeBu and Veloce, including compilation, model configuration, basic connectivity validation and debug. • Support FPGA prototype and emulator debug using waveform/debug tools, FPGA probes, logs and hardware/software correlation. • Analyze RTL and implementation reports to identify synthesis, P&R, timing and emulation-related issues, and work with RTL/DV teams to resolve them. • Work closely with Design, DV, SV, Firmware, Software and Board teams to reproduce, debug and close issues encountered during FPGA prototype and emulator bring-up. • Support prototype/emulator regression execution, analyze failures and ensure issues are properly documented and tracked to closure. • Develop and maintain TCL/Perl/Python automation for FPGA builds, configuration, regression, log analysis, timing/QoR extraction and repetitive debug activities. Registered Office: L&T House, N. M. Marg, Ballard Estate, Mumbai- 400 001. INDIA L& T Semiconductor Technologies Limited is a wholly owned subsidiary of Larsen & Toubro Limited L&T Semiconductor Technologies Limited L&T Tech Park, S-2 Building, 10th Floor, Bellary Road, Next to Raintree Boulevard, Park View Layout, Byatarayanapura, Bengaluru, Karnataka,560092 www.Ltsct.com CIN: U26109MH2023PLC414519 • Monitor and improve FPGA build time, implementation QoR, timing, resource utilization and prototype execution performance. • Support evaluation and adoption of new FPGA boards, prototyping platforms and emulator capabilities under the guidance of senior technical leadership. • Contribute to defining and improving FPGA prototyping and emulation flows, checklists and debug methodologies based on project experience. • Take ownership of assigned technical workstreams and ensure milestones, deliverables and quality objectives are achieved within the project schedule. • Act as a technical point of contact for assigned FPGA/emulation areas, providing status, issues, dependencies and recovery plans to the technical lead. • Mentor junior engineers on day-to-day FPGA prototyping, implementation, bring-up and debug activities. Core Ownership Areas FPGA Prototyping – Primary HAPS | Protium | Multi-FPGA Partitioning | Synthesis | P&R | Timing Closure | Clock/Reset | Bitfile Generation | FPGA Board Bring-up | FPGA Debug | QoR Optimization Emulation – Supporting/Hands-on ZeBu | Veloce | Emulator Model Bring-up | Compilation | Connectivity Validation | Debug | Regression Execution & Productivity RTL Analysis | HW/SW Debug | Regression | Automation | Issue Tracking | Cross-functional Debug | Technical Documentation
Source: Larsen & Toubro careers — Read the original posting and apply
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