Job Description Experience Summary Define ASIC/SoC verification strategy Good understanding of ASIC/SoC life cycle Full chip testplan development Experience writing ASIC/SoC testplans Full chip TB Architecture definition Experience in writing verification strategy document UVM based testbench development 1.Experience in ASIC/SoC Testbench definition 2.Experience to Build and maintain reusable block-level and sub-system testbenches using SystemVerilog and the Universal Verification Methodology (UVM). C based TB development 1. Experience in developing TB components for SOC with C, SV SV functional coverage, Assertions coding 1.Expertise & hands-on experience in OVM/UVM methodologies using SV 2.Experience to Write, execute, and debug constrained-random and directed test cases based on defined test plans. Test case development, coding, execution, bug analysis 1. Experience in developing TB components, including functional coverage implementatio
Source: HCLTech careers — Read the original posting and apply
This role is listed by the employer on its own careers site. Kaam Ki Khoj does not process applications for it.
HCLTech is an employer in the IT/Computers - Software, Software Services sector with operations in India. This is a directory listing maintained by Kaam Ki Khoj so that candidates can find the organisation; it is not an official company page and Kaam... Read More
Upload your CV once — we read it, build your profile and put you in front of every employer hiring on Kaam Ki Khoj. No forms, no fees.
