IP Management Lead - Central Design Methodology / CAD

IP Management Lead — Central Design Methodology / CAD

Role Overview

We are seeking an experienced IP Management Lead to lead and own, with a small team within the Central Design Methodology / CAD organization, the end-to-end management of semiconductor IPs used across Digital and Analog/Mixed-Signal (AMS) SoCs.

The role is responsible for establishing and executing a robust methodology/process for external IP procurement, IP landing/onboarding, quality assessment, qualification, release, repository management, maintenance, and lifecycle governance. The same quality, release, management, and maintenance framework will be applied to internally developed IPs too, in close collaboration with the teams that develop those IPs.

The team will not develop IPs. Instead, it will act as the central team responsible for ensuring that IPs entering the company or being released for SoC reuse meet defined quality, completeness, integration, documentation, configuration, and release criteria.

The role will establish a scalable IP management framework that enables efficient and reliable reuse of IP across multiple Digital and AMS SoC programs.

Key Responsibilities

1. IP Management Strategy & Methodology

• Define and own the company's central IP management methodology covering both external and internal IPs.
• Establish standardized processes from IP procurement/onboarding through qualification, release, reuse, maintenance, and retirement.
• Define IP management policies, procedures, checklists, templates, quality gates, and release criteria.
• Establish consistent IP management practices across Digital and AMS SoC organizations.
• Continuously improve the methodology based on lessons learned from SoC programs and IP suppliers.

2. External IP Procurement & Onboarding

Own the technical/process aspects of external IP procurement and onboarding, working with Procurement, Legal, Architecture, Design, and SoC teams.

Responsibilities include:

• Establish technical requirements and qualification criteria for externally sourced IP.
• Review IP deliverables and supplier documentation.
• Coordinate technical evaluation of candidate IPs with appropriate internal engineering teams.
• Define required deliverables, formats, views, models, documentation, and collateral.
• Establish a standardized IP landing/onboarding process.
• Ensure that all required IP collateral is received, correctly structured, version controlled, and integrated into the company's IP environment.
• Track supplier IP versions, dependencies, licenses, restrictions, and contractual deliverables.
• Establish mechanisms for managing supplier updates, patches, bug fixes, and new IP releases.

3. IP Quality Check & Qualification

Develop and own the central IP quality-check and qualification process for both external and internal IPs.

Define and coordinate appropriate quality gates covering areas such as:

• Functional correctness and completeness
• RTL/source-code quality where applicable
• Simulation models
• Verification collateral
• Synthesis readiness
• Physical implementation readiness
• Timing/power/area information where applicable
• DFT/test collateral
• CDC/RDC and lint requirements
• Formal verification requirements where applicable
• Low-power/UPF requirements where applicable
• AMS simulation/model completeness
• PVT/corner coverage
• Memory/Foundation IP characterization data
• OTP/MTP/Flash and other non-volatile-memory-related collateral
• Technology/PDK compatibility
• Documentation and integration guides
• IP dependencies and required supporting IPs
• Version/configuration consistency

The IP Management team will coordinate and enforce the quality process, while the relevant IP development/engineering teams remain responsible for fixing IP-specific technical issues.

4. Foundation IP Management

Establish dedicated management and qualification processes for Foundation IP, including:

• Standard-cell libraries
• Memory compilers and memory macros
• Other technology-dependent foundational IP

Ensure proper management of:

• Technology/node compatibility
• PVT and characterization data
• Timing and power models
• Physical abstracts/views
• Logical views
• Library collateral
• PDK dependencies
• Version compatibility
• SoC integration requirements
• Release configuration
• Generate PPA optimized memories as required by the SoC

5. Digital IP Management

Manage the lifecycle of Digital IPs used across SoCs, including:

• Processor/CPU-related IP
• Interconnect and NoC IP
• Interface IP
• Security IP
• Controllers
• Peripheral IP
• Digital accelerators
• Other reusable digital functional blocks

Ensure that each IP has the required design, verification, implementation, documentation, and integration collateral before release.

6. AMS IP Management

Establish and manage the corresponding lifecycle process for Analog/Mixed-Signal IPs, including:

• Analog IP
• Mixed-signal IP
• Interface IP
• Data-converter-related IP
• Clocking/PLL-related IP
• Power-management-related IP
• Other AMS reusable blocks

Coordinate with AMS design, verification, modeling, layout, and methodology teams to establish appropriate qualification and release criteria.

7. OTP / MTP / Flash and Non-Volatile IP Management

Own the management methodology for technology-dependent memory and non-volatile IPs such as:

• OTP
• MTP
• Flash
• eFuse and related programmable/non-volatile technologies
• Other technology-specific embedded memory IPs

Ensure appropriate management of technology dependencies, programming models, models/views, characterization data, verification collateral, physical data, and integration requirements.

8. Internal IP Quality, Release & Lifecycle Management

Establish the same central quality and release framework for internally developed IPs.

The IP Management team will:

• Define IP release requirements.
• Perform/coordinate IP quality checks.
• Verify completeness of required deliverables.
• Ensure required documentation and integration collateral are available.
• Validate release configuration and dependencies.
• Assign/manage IP versions and releases.
• Publish qualified IPs for SoC reuse.
• Maintain the IP repository and catalog.
• Monitor released IPs throughout their lifecycle.

The team does not develop the internal IP. Technical ownership remains with the respective IP development organization.

9. IP Release Management

Own the formal IP release process for both external and internal IPs.

Establish controlled release mechanisms including:

• Release criteria
• Release checklists
• Versioning
• Configuration management
• Release approval
• Dependency validation
• Release notes
• Known-issue tracking
• Documentation
• Integration collateral
• Approved/qualified status
• Release traceability

Ensure that SoC teams consume controlled and qualified IP releases rather than uncontrolled development versions.

10. IP Repository, Database & Catalog Management

Own the central IP repository and IP information infrastructure.

Establish a single source of truth for:

• IP identity
• IP type/category
• Version
• Owner/development organization
• Supplier
• Technology/node
• Supported SoC platforms
• Qualification status
• Release status
• Dependencies
• Required EDA views/models
• Documentation
• Licensing information
• PDK/technology dependencies
• Known issues
• Change history
• Approved usage
• Obsolescence/retirement status

Develop an effective IP catalog/search capability so SoC teams can quickly identify and reuse qualified IP.

11. IP Configuration & Dependency Management

• Establish configuration-management methodology for complex IPs and IP platforms.
• Manage dependencies between IPs, libraries, models, PDKs, tools, and technology versions.
• Ensure that an IP release represents a consistent and reproducible configuration.
• Provide impact analysis when IP, PDK, EDA tool, or technology versions change.
• Prevent incompatible combinations of IP collateral from being released for SoC use.

12. IP Maintenance & Sustenance

Own the lifecycle management of released IPs.

Activities include:

• Tracking IP issues and quality status.
• Managing IP updates and revisions.
• Coordinating supplier updates for external IP.
• Coordinating fixes with internal IP development teams.
• Managing backward compatibility where required.
• Maintaining documentation and integration collateral.
• Managing obsolete or deprecated IP versions.
• Communicating IP changes and release updates to SoC teams.
• Ensuring continued usability of IP across supported SoC programs.

13. EDA/CAD & Design Infrastructure Integration

Work closely with the Central CAD/EDA and Design Methodology teams to ensure IP management is integrated with the company's design infrastructure.

Areas include:

• Cadence
• Synopsys
• Siemens EDA
• Git/source-control environments
• IP repositories
• IP-XACT where applicable
• PDK infrastructure
• CI/CD infrastructure
• Simulation and verification environments
• Synthesis and implementation flows
• DFT infrastructure
• AMS design environments
• Package/physical-design collateral where applicable

Establish automated IP validation and release flows wherever practical.

14. Automation & AI-Based IP Management

Drive automation of IP management activities using scripting, databases, AI/ML, and AI agents.

Potential automation areas include:

• Automatic IP collateral completeness checks
• Metadata extraction
• IP catalog generation
• IP version/configuration validation
• Dependency analysis
• Change-impact analysis
• Automated release-readiness checks
• Automated quality-gate execution
• IP documentation generation
• IP reuse/discovery
• Similar-IP identification
• IP qualification dashboards
• Supplier IP update analysis
• Automated release-note generation
• Continuous monitoring of IP quality and status

Where commercial tools do not provide the required capability, work with the Central Design Methodology/CAD/AI teams to develop custom automation and AI-agent solutions.

15. IP Metrics & Quality Dashboard

Establish metrics and dashboards to monitor the health of the IP ecosystem, such as:

• Number of qualified/released IPs
• IP quality status
• IP reuse
• IP release cycle time
• External IP onboarding time
• IP qualification status
• Open IP issues
• IP update/maintenance status
• IP versions in active SoCs
• Obsolete/deprecated IPs
• Supplier quality metrics
• IP-related SoC integration issues
• IP reuse efficiency

Use these metrics to identify systemic problems and drive continuous improvement.

16. Cross-Functional Leadership

Work closely with:

• Digital Design
• AMS Design
• RF Design
• SoC Architecture
• Verification
• Physical Design
• DFT
• CAD/EDA
• Central Design Methodology
• PDK/Technology teams
• Procurement
• Legal/IP Licensing
• External IP suppliers
• SoC Program Management

Act as the central point of coordination for IP lifecycle and release-related activities.

Organization & Team Scope

The role will lead a small centralized IP Management team within the Central Design Methodology organization.

The team owns the IP management process and infrastructure, not IP development.

IP Development Teams

Responsible for:

• IP architecture
• IP design/development
• IP-specific verification
• IP-specific bug fixing
• Technical ownership of the IP

Central IP Management Team

Responsible for:

• IP procurement/onboarding
• IP landing
• Quality-check methodology
• Qualification coordination
• Release management
• Repository/catalog management
• Configuration/dependency management
• Lifecycle management
• Maintenance/sustenance coordination
• IP governance
• Automation and infrastructure

This separation establishes clear accountability while providing SoC teams with a centrally managed pool of qualified, reusable IP.

Required Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
• Typically 15+ years of semiconductor/SoC/IP experience, with significant experience in IP or design methodology.
• Strong understanding of Digital and/or AMS SoC development flows.
• Experience working with reusable semiconductor IP.
• Experience with IP qualification, release, configuration, and lifecycle management.
• Understanding of RTL, verification, synthesis, physical design, DFT, and/or AMS flows.
• Experience with semiconductor EDA environments and design infrastructure.
• Strong understanding of IP dependencies, technology/PDK dependencies, and configuration management.
• Experience working with external IP suppliers/vendors.
• Strong cross-functional and technical leadership skills.

Preferred Qualifications

• Experience managing Foundation IP, Digital IP, AMS IP, and embedded NVM IP.
• Experience with Standard Cell and Memory IP.
• Experience with OTP/MTP/Flash/eFuse or similar technology-dependent IP.
• Experience with IP-XACT and structured IP metadata.
• Experience with IP repositories and database-driven IP management.
• Experience with Git, CI/CD, scripting, and design-flow automation.
• Experience with Cadence, Synopsys, and/or Siemens EDA environments.
• Experience implementing automated IP quality/release checks.
• Experience with AI/ML or AI-agent-based engineering automation.
• Experience managing IP across multiple SoC programs and technology nodes.

Leadership Competencies

• Strong ownership and accountability.
• Ability to establish and drive organization-wide methodology.
• Strong semiconductor design-flow understanding.
• Ability to work across Digital, AMS, RF, Physical Design, Verification, DFT, CAD, and Technology organizations.
• Strong vendor and external IP management skills.
• Ability to distinguish IP technical ownership from IP lifecycle/process ownership.
• Strong process and quality mindset.
• Ability to drive automation and continuous improvement.
• Excellent communication and stakeholder-management skills.

Success Measures

Success in this role will be demonstrated by establishing a scalable IP ecosystem in which:

• External IP can be onboarded efficiently and consistently.
• Internal IP can be released through a standardized qualification process.
• Only qualified and approved IP releases are made available for SoC reuse.
• IP versions and dependencies are controlled and traceable.
• IP quality issues are identified early, before SoC integration.
• SoC teams can easily discover and reuse qualified IP.
• IP maintenance and updates are systematically managed.
• IP-related integration risk and duplicated effort are reduced.
• IP management activities become increasingly automated.
• A reliable central IP repository/catalog and single source of truth is established for Digital and AMS SoC development.

Role Summary

The IP Management Lead is the central owner of the IP supply chain and lifecycle—from external IP procurement and landing, through quality qualification and controlled release, to repository management, maintenance, and reuse—for both externally sourced and internally developed IPs.

The role does not develop IPs; it establishes the methodology, governance, infrastructure, quality gates, and automation that ensure IPs are qualified, controlled, reusable, and ready for SoC integration.

Job details

• Business: L&T Semiconductor Technologies Limited
• Location: Bengaluru, Karnataka
• Experience: 15-30 years
• CTC range: ₹70,00,000 – ₹90,00,000 a year
• Skills: Analog and Mixed signal Verification, Digital Designs, RF design, Analog Circuit Design