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DTMA & Memory Controller Design Lead

Date Posted: Aug 27, 2026
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    Location Bengaluru, Karnataka, India
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    Job Type: Full Time/Permanent
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    Apply Before: Nov 14, 2026
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Job Description

DTMA & Memory Controller Design Lead

Location: Bangalore, India | Company: LTSCT — L&T Semiconductor Technologies Limited

Reporting To: Chandra — Senior Architect, DC HW Systems | Experience: 10+ years (mandatory)

Role Summary

The DTMA & Memory Controller Design Lead owns the Data Transfer and Memory Access (DTMA) engine together with HBM4e memory-controller integration. You will orchestrate all data movement between the 512-bank SRAM (8 TB/s), the 6-stack HBM4e subsystem (384 GB, 12 TB/s), and the PE arrays — the subsystem that keeps xPU's compute engine saturated.

Key Responsibilities

  • Own micro-architecture and RTL of the DTMA engine managing data movement between SRAM banks, HBM4e, and the BFOS PE arrays.
  • Define the compute-to-memory interface with the DTMA engine and SRAM banks to keep PE arrays fully fed at bandwidth.
  • Lead integration and configuration of HBM4e memory controllers across 6 stacks (384 GB, 12 TB/s aggregate).
  • Design descriptor-based DMA, gather/scatter, tensor-tiling, and prefetch mechanisms optimized for BFOS dataflow.
  • Architect the 512-bank, 8 TB/s SRAM access scheduling, bank arbitration, and conflict-avoidance logic.
  • Optimize address mapping, request scheduling, and refresh/timing to maximize sustained HBM bandwidth efficiency.
  • Define QoS and flow-control interfaces to the NoC and compute engine to prevent stalls and starvation.
  • Drive verification, performance modeling, and bandwidth/latency closure across realistic AI workload traffic.
  • Collaborate with PD on HBM PHY/controller placement and with architecture on memory-hierarchy trade-offs.

Required Skills & Experience

  • 10+ years in memory-subsystem, DMA, or memory-controller design for high-bandwidth SoCs.
  • Deep expertise with DRAM/HBM controller architecture, scheduling, and timing (HBM2E/HBM3/HBM3E; HBM4e a strong plus).
  • Strong RTL (SystemVerilog) design skills for DMA engines, arbiters, and memory schedulers.
  • Solid understanding of multi-bank SRAM architectures, banking/interleaving, and conflict resolution.
  • Experience with descriptor-based DMA, gather/scatter, tensor tiling, and prefetching.
  • Knowledge of address mapping, request reordering, and bandwidth/efficiency optimization.
  • Familiarity with AI/ML data-movement patterns and their impact on memory-system design.
  • Hands-on performance modeling and closure for high-bandwidth memory subsystems.
  • Proficiency in C/C++/Python for modeling and verification.
  • Proven technical leadership and cross-functional collaboration.

Preferred Qualifications

  • Experience integrating HBM PHY/controller IP on advanced nodes.
  • Background in AI accelerator or HPC memory subsystems.
  • Familiarity with UCIe/NoC traffic interaction with memory controllers.
  • M.Tech/MS in EE/ECE or equivalent.













Job details

  • Business: L&T Semiconductor Technologies Limited
  • Location: Bengaluru, Karnataka
  • Experience: 10-18 years
  • Skills: Memory Controllers, Design

Source: Larsen & Toubro careers — Read the original posting and apply

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Company Overview

Larsen & Toubro
Larsen & Toubro · Mumbai, Maharashtra, India
400 open roles

Larsen & Toubro is an employer in the Construction/Engineering sector with operations in India. This is a directory listing maintained by Kaam Ki Khoj so that candidates can find the organisation; it is not an official company page and Kaam Ki Kh... Read More

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