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DFT Engineer

Date Posted: Sep 10, 2026

Job Detail

  • location_on
    Location Bengaluru, Karnataka, India
  • desktop_windows
    Job Type: Full Time/Permanent
  • schedule
    Shift:
  • analytics
    Career Level:
  • group
    Positions:
  • calendar_view_day
    Experience:
  • male
    Gender: No Preference
  • school
    Degree:
  • calendar_month
    Apply Before: Nov 08, 2026

Job Description

Job Description

Lead DFT architecture and test strategy definition for advanced SoCs, ensuring high-quality manufacturing testability and diagnosis readiness.

Job Description - Grade Specific

Key Responsibilities

  • Define SoC DFT architecture.
  • Establish ATPG, scan, MBIST, LBIST strategies.
  • Drive test coverage objectives.
  • Define compression and diagnosis methodologies.
  • Work with RTL, Verification, and Physical Design teams.
  • Review DFT signoff requirements.
  • Interface with customer test and manufacturing organizations.

Must Have

  • 12+ years of DFT experience.
  • Multiple successful SoC tapeouts.
  • Good Knowledge on RISC and ARM SoC DFT strategy for sub-systems and top level
  • Expertise in scan insertion and ATPG.
  • Strong understanding of MBIST/LBIST.
  • Experience with Tessent and/or Synopsys DFT tools.
  • Knowledge of test compression and diagnosis.
  • Understanding of JTAG and IEEE 1500/1687.

Good to Have

  • Safety DFT.
  • Automotive test methodologies.
  • Silicon bring-up support experience.
  • Yield learning and diagnosis.
  • Chiplet test architecture.
  • Advanced node test challenges.

Source: Capgemini careers — Read the original posting and apply

This role is listed by the employer on its own careers site. Kaam Ki Khoj does not process applications for it.

Company Overview

India

Capgemini openings shown on Kaam Ki Khoj are read directly from the company's own careers site and link back to it. Apply there; Kaam Ki Khoj does not process applications for these roles and is not affiliated with Capgemini. Read More

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