Full chip TB Architecture definition Experience writing ASIC/SoC testplans
UVM based testbench development
1.Experience in ASIC/SoC Testbench definition
2.Experience to Build and maintain reusable block-level and sub-system testbenches using SystemVerilog and the Universal Verification Methodology (UVM)."
SV functional coverage, Assertions coding
1.Expertise & hands-on experience in OVM/UVM methodologies using SV
2.Experience to Write, execute, and debug constrained-random and directed test cases based on defined test plans.
C based TB development
1. Experience in developing TB components for SOC with C, SV
Test case development, coding, execution, bug analysis
1. Experience in developing TB components, including functional coverage implementation and assertion coding
2. Experience Set up functional coverage, write system assertions (SVA), and analyze code coverage metrics to identify untested gaps in the design logic.
3.Debug complex simulation failures using waveform viewer tools to isolate design bugs from testbench issues.
4. Experience in SOC C based tests coding & debugging
Gate Level Simulation
Experience in Gate level simulation & netlist debugging
Regressions, coverage analysis
Experience in regression failure analysis
Functional and Code Coverage closure
participate in verification closure
Experience in Perl/Shell scripting
Full chip TB Architecture definition Experience writing ASIC/SoC testplans
UVM based testbench development
1.Experience in ASIC/SoC Testbench definition
2.Experience to Build and maintain reusable block-level and sub-system testbenches using SystemVerilog and the Universal Verification Methodology (UVM)."
SV functional coverage, Assertions coding
1.Expertise & hands-on experience in OVM/UVM methodologies using SV
2.Experience to Write, execute, and debug constrained-random and directed test cases based on defined test plans.
C based TB development
1. Experience in developing TB components for SOC with C, SV
Test case development, coding, execution, bug analysis
1. Experience in developing TB components, including functional coverage implementation and assertion coding
2. Experience Set up functional coverage, write system assertions (SVA), and analyze code coverage metrics to identify untested gaps in the design logic.
3.Debug complex simulation failures using waveform viewer tools to isolate design bugs from testbench issues.
4. Experience in SOC C based tests coding & debugging
Gate Level Simulation
Experience in Gate level simulation & netlist debugging
Regressions, coverage analysis
Experience in regression failure analysis
Functional and Code Coverage closure
participate in verification closure
Experience in Perl/Shell scripting
Source: HCLTech careers — Read the original posting and apply
This role is listed by the employer on its own careers site. Kaam Ki Khoj does not process applications for it.
HCLTech is an employer in the IT/Computers - Software, Software Services sector with operations in India. This is a directory listing maintained by Kaam Ki Khoj so that candidates can find the organisation; it is not an official company page and Kaam... Read More
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